1. Field of the Invention
This invention relates to design of semiconductor integrated circuits, and more particularly to an automatic layout design method and system.
2. Description of the Prior Art
CAD (Computer Aided Design) or DA (Design Automation) has become indispensable for design of large-scale integrated circuits. Automation of a logic design process has made a progress in recent years and studies have been made vigorously on a system for automatically synthesizing a circuit using real logic elements on the basis of abstract logic description. Japanese Patent Laid-Open No. 167060/1985, for example, describes a method of automatically synthesizing a logic from structure
information and behavior information. Japanese Patent Laid-Open No. 88371/1986 discloses a method of synthesizing a logic circuit of desired technology from the description of behavior characteristics.
In the field of automatic layout design, on the other hand, a technique of determining the physical positions of real logic elements (cells) on the basis of connection information of the cells and carrying out automatic wiring between these cells has been put into practical use. In this automatic cell placement processing, iterative refinement of the cell positions is generally conducted so as to primarily minimize an imaginary wiring length.
According to this iterative refinement processing, final placement result will become good if initial placement positions are determined excellently. Therefore, processing for determining the initial placement positions has been examined. For example, Proc. of 9th Design Automation Conference, pp. 50-56, describes the initial placement position determination processing which is referred to as a "clustering method".
Furthermore, "The institute of Electronics & Communication Engineers, Technical Report" CAS-854(1984) "Circuit and System" describes that a good placement result can be obtained by taking the flow of logic of a logic structure into specific consideration when this initial placement position is determined. As the problem to be solved in order to automate the layout for preserving the logic structure, this report mentions a large waste region in this placement result and proposes to arrange the block shape by moving the cells.
According to the conventional methods described above, however, it has been necessary to designate manually the logic structure and to designate manually the relative position relation of the cells so that the number of man-hour is great. In accordance with the method which first makes placement in accordance with the logic structure and then moves the cells to arrange the block shape, the flow of data is disturbed and this method cannot be automated so readily as the layout method having high performance.